MUX_A8=MUX_A8_0, MUX_RDY=MUX_RDY_0, MUX_CSX2=MUX_CSX2_0, MUX_CSX3=MUX_CSX3_0, MUX_CSX1=MUX_CSX1_0, MUX_CSX0=MUX_CSX0_0
IO Mux Control Register
| MUX_A8 | SEMC_A8 output selection 0 (MUX_A8_0): SDRAM Address bit (A8) 1 (MUX_A8_1): NAND CE# 2 (MUX_A8_2): NOR CE# 3 (MUX_A8_3): PSRAM CE# 4 (MUX_A8_4): DBI CSX 5 (MUX_A8_5): SDRAM Address bit (A8) 6 (MUX_A8_6): SDRAM Address bit (A8) 7 (MUX_A8_7): SDRAM Address bit (A8) |
| MUX_CSX0 | SEMC_CSX0 output selection 0 (MUX_CSX0_0): NOR/PSRAM Address bit 24 (A24) 1 (MUX_CSX0_1): SDRAM CS1 2 (MUX_CSX0_2): SDRAM CS2 3 (MUX_CSX0_3): SDRAM CS3 4 (MUX_CSX0_4): NAND CE# 5 (MUX_CSX0_5): NOR CE# 6 (MUX_CSX0_6): PSRAM CE# 7 (MUX_CSX0_7): DBI CSX |
| MUX_CSX1 | SEMC_CSX1 output selection 0 (MUX_CSX1_0): NOR/PSRAM Address bit 25 (A25) 1 (MUX_CSX1_1): SDRAM CS1 2 (MUX_CSX1_2): SDRAM CS2 3 (MUX_CSX1_3): SDRAM CS3 4 (MUX_CSX1_4): NAND CE# 5 (MUX_CSX1_5): NOR CE# 6 (MUX_CSX1_6): PSRAM CE# 7 (MUX_CSX1_7): DBI CSX |
| MUX_CSX2 | SEMC_CSX2 output selection 0 (MUX_CSX2_0): NOR/PSRAM Address bit 26 (A26) 1 (MUX_CSX2_1): SDRAM CS1 2 (MUX_CSX2_2): SDRAM CS2 3 (MUX_CSX2_3): SDRAM CS3 4 (MUX_CSX2_4): NAND CE# 5 (MUX_CSX2_5): NOR CE# 6 (MUX_CSX2_6): PSRAM CE# 7 (MUX_CSX2_7): DBI CSX |
| MUX_CSX3 | SEMC_CSX3 output selection 0 (MUX_CSX3_0): NOR/PSRAM Address bit 27 (A27) 1 (MUX_CSX3_1): SDRAM CS1 2 (MUX_CSX3_2): SDRAM CS2 3 (MUX_CSX3_3): SDRAM CS3 4 (MUX_CSX3_4): NAND CE# 5 (MUX_CSX3_5): NOR CE# 6 (MUX_CSX3_6): PSRAM CE# 7 (MUX_CSX3_7): DBI CSX |
| MUX_RDY | SEMC_RDY function selection 0 (MUX_RDY_0): NAND Ready/Wait# input 1 (MUX_RDY_1): SDRAM CS1 2 (MUX_RDY_2): SDRAM CS2 3 (MUX_RDY_3): SDRAM CS3 4 (MUX_RDY_4): NOR CE# 5 (MUX_RDY_5): PSRAM CE# 6 (MUX_RDY_6): DBI CSX 7 (MUX_RDY_7): NOR/PSRAM Address bit 27 |